curious_engineer
Junior Member level 2
I am having trouble deciding the architecture for an amp to be used as an integrator for a sigma-delta ADC.
The supply is 1.2V. Does this rule out folded cascode? My idea was to make it one-stage in order to reduce the number of poles, but I don't know if its feasible w/ the limited supply. Maybe a typical miller compensated two stage (differential pair + CS) is better...
Also, with a high oversampling rate, wouldnt the clock frequency be so high that I would need to have this amp settle super fast in switched capacitor feedback configuration? That makes the design requirements fairly stringent I would think.
The supply is 1.2V. Does this rule out folded cascode? My idea was to make it one-stage in order to reduce the number of poles, but I don't know if its feasible w/ the limited supply. Maybe a typical miller compensated two stage (differential pair + CS) is better...
Also, with a high oversampling rate, wouldnt the clock frequency be so high that I would need to have this amp settle super fast in switched capacitor feedback configuration? That makes the design requirements fairly stringent I would think.