Question: LVDS driver input stage

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bluestatic

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lvds driver design

I'm doing a LVDS driver design, which basically is a differential amp, the input of this diff amp is a single-end signal A and its inversion NA. (swing from 0V to 3.3V)

NA is generated from A by using an inverter, so there is a delay time (or skew) between them, let's say, 400ps. Here come the problem, from the simulation I can see that this 400ps skew can cause very seriouse spike on output current. And sometimes it cause output common mode changes.

So I'm wondering if anyone knows how to generated a fully complementary pesudo differental pari from one single end input A.

many thanks
 

lvds input + simulation

u can use a dummy transmission gate to offset the 400ps delay.

also, it sounds like you don't have a predriver for the lvds driver. That's why you have spike.

here is what I have done before and achieved over 1.2G in 0.35um

side1: small inverter+t gate + larger inverter
side2: small inverter+inverter + larger inverter

side1 feeds to a predriver and side2 also feeds to another predriver

i attached a peper,not my design, and u can get a look.
 
weak cross coupled inverter

dumbfrog, sorry I didn't make it very clear. This is an LVDS driver, the input from core is 1G bps single end signle, and LVDS driver buffer will convert it become LVDS signaling.
The question is that I have to make this "signal end input" from core become pesudo diffential, and connect them to the input of diffential amp(LVDS driver). It is very similiar to the previouse question you have answered.
But I have done some simulation on your Tranmssion gate proposal, the result is not so good in high speed. As you know the T gate is basically a resistor, while a inverter is more like an cap. So considering process and temp varation, the T gate compensation may be not so good.
Any comment? Thanks
 

two-stage operational amplifier lvds -patent

A weak cross-coupled inverters placed
between two main inverters will mininimize
the skew between the two signal and make them
pseduo differential. Hope it helps.

Another question:How to control the common
mode voltage of the LVDS driver output?

BR

eric
8/15
 

voltage mode lvds driver application

Eric, I don't really understand your idea, can you give more info on it?
BTW, you can find the link below, it mentioned a way to control driver common mode, and it works in pratical design.

ee.unipr.it/~andrea/PUBLIC/36ssc04-boni.pdf
 


I only know two methods:

The most common way to do it is to place a 10K resistor at the output and use a bandgap (1.2V)+opamp buffer to force the middle of the 10K resistor. Exactly like Fig 2 of bluestatic's attached paper.

The other method is a little complicate, use a dummy current reference to force the 1.2V output.

if any1 know there are better ways to do it, please share it with dumbfrog.
 

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