pig8190
Newbie level 4
1. Design two frequency divide-by-3 circuits, one with output div3a (33% duty cycle), the other with output div3b (50% duty cycle). You can use rising-edge and falling-edge FFs in your designs.
Write the verilog code to generate div3a and div3b. Write a test fixture and capture the waveform. thanks!!!!!!!!
Write the verilog code to generate div3a and div3b. Write a test fixture and capture the waveform. thanks!!!!!!!!