question : folded cascode with 30V and 5V nmos transistors

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cmos_ajay

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Hello, I have attached a folded cascode amplifier with class AB stage picture which is commonly seen in text books. I would like to know :

* Supply VDD = 15v. On the NMOS side, the cascode nmos (M1C, M2C) are 30V devices and the bottom nmos (M5, M6 ) are only 5V devices. What is the special reason to do this ??

* There is also a cascode compensation (indirect frequency compensation) using capacitors CM1 and CM2. Why does this type of compensation eliminate the unwanted zero ? Why does it help in splitting the poles in much better than the standard Miller compensation ? Is there a logical or analytical explanation for this ?

Thanks.
 

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1. The M5,6 fets will has small drain-source voltage even for large signal behaviour (its drain potentials changes are smaller than output variation around (gmro)^2 times)

2. The analytical expressions for cascode compensation can You found in classic papers from Ahuja, Fisher or Ribner and Copeland.
In fact You get 3 poles and 2 zeros but after proper cascode design it could reduce to 2 poles and one very high freq. zero.


Here You have proper articles:

**broken link removed**
**broken link removed**
**broken link removed**
 
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    erikl

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Is there a logical explanation for the cascode compensation benefits ? I am aware of the equations.
 

Cascode compensation provides better PSRR and requier smaller compensation capacitor than Miller one so You get an additional benefit with GBW and SR.
The only drawback is that it provides more poles and zeros which could be complex, but after proper design a very nice two poles system could be achieved.

Ewerything are in linked articles.
 

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