[question] clock gating cell

[gerade]

clock_gating rtl

Hi, All,

Currently we encounter a problem with clock gating cell. Synplify always adds an AND gate behind the latch, the inputs to the AND are a global clock(usually with iso suffix) and the clock generated from the latch.

the VHDL is shown below,

library ieee;
use ieee.std_logic_1164.all;

entity clock_gating is
port (
CPEN : out std_ulogic;
CP : in std_ulogic;
EN : in std_ulogic;
TE : in std_ulogic
);
end clock_gating;


architecture rtl of clock_gating is

signal latch_enable_s : std_ulogic;
signal clk_latched_s : std_ulogic;
signal clk_enable_s : std_ulogic;

begin

-- OR gate for TE before clock gating latch
latch_enable_s <= EN or TE when (latch_enable_with_test_enable_c = TRUE) else
EN;

-- Clock gating latch
clock_gating_latch : process (CP, latch_enable_s)
begin
if (CP = '0') then
clk_latched_s <= latch_enable_s;
end if;
end process clock_gating_latch;

-- OR gate for TE after clock gating latch
clk_enable_s <= clk_latched_s or TE when (latch_enable_with_test_enable_c = FALSE) else
clk_latched_s;

-- Clock gating through AND gate
CPEN <= CP and clk_enable_s;

end rtl; -- of clock_gating

This RTL works well with simple design with set_option -fixgatedclocks 3 in prj file and with a simple clock define constraints to define the source clock, but not in complex design, like 2 level clock gating structure, which means a clock derives from another gated clock.

did anyone meet similar problem before and any suggestion?

Thanks in advance!

Gerade

Added after 19 minutes:

This issue makes it impossible for us to add timing constraints for synthesis and have to auto-constraint the design. Therefore the result after synthesis is quite lousy and make the P & R very difficult and unstable.

In P & R, we still can not add timing constraints like clock definition(except for external clock) and multi-cycle path etc.

 

[gerade]

gating cell

can anyone give me a hand?

 

[r_e_m_y]

clock gating cell code

Hi gerade,

When you write :

clock_gating_latch : process (CP, latch_enable_s) 
begin 
  if (CP = '0') then 
    clk_latched_s <= latch_enable_s; 
  end if; 
end process clock_gating_latch;

I understand that you want to latch the value of latch_enable_s on falling edge of CP and on each change of latch_enable_s when CP is low.
It is difficult to imagine the synthesized solution for this code.

If only the falling edge of CP is needed to latch your signal, try with this code :

clock_gating_latch : process (CP) 
begin 
  if falling_edge(CP) then 
    clk_latched_s <= latch_enable_s; 
  end if; 
end process clock_gating_latch;

may be this will help synplify to generate always the same rtl.