elbadry said:
I think the point is that M1, M2, M3 and M4 form a translinear loop which is characterized by:
Vgs1 + Vgs2 = Vgs3 + Vgs4
Hence if Vgs1,2 = Vgs3 ---> Vgs4 = Vgs1 ( as if the output transistor is having a mirror current from M1 )
As you need the NMOS and PMOS currents (of the output ) to be equal, you have to make currents in M3,M7 equal to those in the diode connected NMOS and PMOS branches.
I think that if in the end you get the current you want in the output branch, then you do not have to bother about the two current being equal.
i.e. In the end, you want the output current = k*current in diode stack
where K is a mirroring factor
Here is what I find out:
The idea of those translinear loops, M1 to M4 and M5 to M8, is to give the two output transistors "small but well control idle current to minimize any uneven behavior as the output signal is switched from one transistor to the other" [1]. However, according to my simulation, the idle current is hardly well controled. I cann't see any relation between the output idle current and the two 5uA current source.
Actually the idle current is controled by the gate voltages of both M8 and M4, these two voltages are not really well controled by M3 and M7 because the current of M3 and M7 is not well defined. If their currents are fixed to half of the tail current, then the Vgs of both M3 and M7 are defined, but since the drain voltages of M9 and M10 are very losse, their final value, Vin1 and Vin2, are controled by the strong feedback loop. I would say M3 and M7 do have some contribution of fixing Vin1 and Vin2, but their effect are not very strong. In fact, the currents of M3 and M7 are controled by Vin1 and Vin2, not the other way round. Thus the result is, currents of M3 and M7 are very unlikely to be equal. For most cases, one of them conducts most current and the other one operates in sub-threshold--it is dead!
To tune the currents of M3 and M7, we can tune the size of the two output transistors M4 and M8 because it is the feed back loop fixs their current (M3 and M7)
assuming that their gate voltages are properly biased. Let say the current of M3 is much larger than that of M7, then reduce the W/L of M4 (to raise Vin2) or increase W/L of M8 (to raise Vin1). This is very effective and you can also tune the output idle current at the same time.
The point of M3 and M7 here should be: to give the two output transistors
small idle current to minimize any uneven behavior as the output signal is switched from one transistor to the other. M3 and M7 are not much better than a simple resistor I think (if we can make the resistor small). How to control this idle current? I think we have to tune the size of the output transistors. Again, not much control on it.
[1] Hans Camenzind, "Designing Analog Chips"
**broken link removed**