outputting two differential signals "Data out" and "DDR Clk" from the FPGA to another chip
"Shift the clock phase easily" -- are you attempting to output "Data out" and "DDR Clk" with a precise, adjustable delay between them?
"Register to capture the data" -- are you referring to a register in the external device that receives "Data out" and "DDR Clk"?
module top (iclk, odatap, odatan, oclkp, oclkn);
(* LOC="T9", PERIOD="50MHz" *) input iclk; // oscillator
wire clk;
wire clk0dcm, clk0;
reg [17:0] lfsr = 0;
wire odata;
(* LOC="B10" *) output odatap; // A2 pin 27
(* LOC="A10" *) output odatan; // A2 pin 28
wire oclk;
(* LOC="A4" *) output oclkp; // A2 pin 18
(* LOC="B4" *) output oclkn; // A2 pin 17
BUFG buf0 (.I(iclk), .O(clk));
FDDRCPE ff0 (.C0(clk), .C1(~clk), .D0(lfsr[0]), .D1(lfsr[1]), .Q(odata), .CE(1'b1), .CLR(1'b0), .PRE(1'b0));
OBUFDS_LVDS_25 u0 (.I(odata), .O(odatap), .OB(odatan));
DCM dcm1 (.CLKIN(clk), .CLKFB(clk0), .CLK0(clk0dcm), .RST(1'b0));
defparam dcm1.CLK_FEEDBACK = "1X";
defparam dcm1.CLKIN_PERIOD = 20.0;
defparam dcm1.CLKOUT_PHASE_SHIFT = "FIXED";
defparam dcm1.PHASE_SHIFT = 26; // clock 2ns after data
BUFG buf1 (.I(clk0dcm), .O(clk0));
FDDRCPE ff1 (.C0(clk0), .C1(~clk0), .D0(1'b1), .D1(1'b0), .Q(oclk), .CE(1'b1), .CLR(1'b0), .PRE(1'b0));
OBUFDS_LVDS_25 u1 (.I(oclk), .O(oclkp), .OB(oclkn));
always @ (posedge clk) begin
lfsr <= {lfsr, lfsr[17] ~^ lfsr[10], lfsr[16] ~^ lfsr[9]};
end
endmodule
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