Question about vias that pass through plane layers

[OradFarez]

remove unconnected pad plane

I have numerous vias that are very close together (under a BGA chip with 0.5mm pin pitch). They are 0.2mm outer ring with a 0.1mm hole.

There isn't much room for large plane swells and if I try to make them large they all run together and create a voided line in the plane that can cut off areas of the plane.

My question is about what the pad area looks like on the plane layers? All holes are plated and through (no blind/buried). The output gerber file shows that the entire pad area is voided of copper (plus a bit extra), but doesn't there need to be something around the hole for the plating to stick and pass down to the next layer? I admit I don't know exactly how the plating process works. I have never questioned it before as this is the first board I have done with this kind of density.

Right now I have the swell set to create a circular void of 0.355mm which is acceptable if board manufacturers don't leave any copper around the hole despite the files I send them.

Can someone help me understand the process better please? Thank you!

 

[touringmike]

My question is about what the pad area looks like on the plane layers? All holes are plated and through (no blind/buried). The output gerber file shows that the entire pad area is voided of copper (plus a bit extra), but doesn't there need to be something around the hole for the plating to stick and pass down to the next layer? I admit I don't know exactly how the plating process works

No annular rings are required on the internal layers if the signal doesn't make a connection on that particular layer. (wether they be trace layers- positive, or plane layer-negative)

The board layers are drilled before the plating process for plated through holes. Most all board manufacturers will remove unconnected pads on internal trace layers, and the plating process works quite well. The copper plating process of a multilayer board is an emmersion wet process, so the copper flows through the holes of the board, and makes a connection to the internal layer pads were the signal is used.

Unplated holes are processed after the plating of the board is done.

 

[OradFarez]

Thank you very much for the detailed explanation! I feel confident my design will be manufactured just as it appears on the screen now.

 

[Hasan Jawed Baig]

Hey ....... actually in multilayer PCBs, the substrate are first drilled because we have to plate the hole with copper in order to connect the layers electrically with each other. In this process, boards are first drilled and then Plated by electrolysis process. In which copper substrate, whose holes have to be plated with copper, acts as cathode while we have two copper anode. On passing the current, copper from anode starts geting deposit on the substrate as well as inside the hole. In this way the copper boards are plated, and the thickness of plating depends upon the duration of board in the electrolytic solution and also upon the quantity of current passed.

i hope the process will be cleared to you.

 

[OradFarez]

so are you saying that there could be a small amount of copper deposited around the hole creating an annular ring? If yes, any idea how wide would this ring be around the hole?

 

[Hasan Jawed Baig]

no no..... now listen me carefully.. i m telling you,, how to plate the vias of double sided PCBs,which in extension forms multilayer boards
you have your substrate ( copper cladding on both the sides ) which is not etched by the solution of Ferric chloride. suppose you just have bought a substrate with copper cladding on both sides. now you first have to drill the board by the help of Drill layer,generated by using gerber tool.

Now, after drilling you will be having a drilled susbtrate with copper present on both sides. Keep in mind that you have to fill these VIAS with copper so that there will be a path for current to enter from top layer to bottom layer. okay?

and i have explained you the process of plating the VIAS with copper.

now .... you are talking about the annular ring ...... this can be widen in OrCAD Layout. Go into Padstacks spread sheet, click on bottom/top layer. press Ctrl+E or press right mouse click and select the properties. A window will appear in front of you, select the Annular ring from radio button ,, and in the last set the PAD WIDTH and PAD HEIGHT according to your requirement.

Added after 7 minutes:

and in the plating process, the copper deposits,not only on the side of the hole, but it deposits on the whole board as well as penetrate in the hole and stuck on the walls of the hole. In this way the hole walls gets plated with copper, making a path for current to flow.