Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Question about VIA overhang.

Status
Not open for further replies.

Woomos

Newbie level 4
Newbie level 4
Joined
May 19, 2022
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
65
Hi, I had a question about VIA overhang while I was studying.

I know that VIA overhang is a parameter that is set to improve the yield of VIA.
When drilling VIA in the process, it makes sense to apply an overhang to the upper layer because the shape of the VIA becomes trapezoidal.
However, I did not understand why the overhang is applied to the lower layer as well.

Any comments or information would be appreciated.
Thank you for read.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top