Question about using voltage doubler

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husseinadel

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hello

i am designing a lvds output buffer ,,the input to it must be swing from '0' to '3.3v',,but the input from the core of the ic has swing from '0' to '1.8',,so i think that using a voltage doubler to accomplish this ,,but i want it for very high speed about 1 Gbps,,,so,,, if i use voltage doubler ,can it work on this speed ??,,,please i want also any papers or books or lectures talking about this issues,,,,,,thanks a lot

regards

hussein
 

voltage doubler

i could suggest instead of using something to convert the voltage, you could use a transistor that will turn on when a voltage of 1.8V is applied and an output of 3.3V, but im not sure if a transistor would work at that speed, probably check some data sheets instead
 

Re: voltage doubler

Wouldn't a 1.8 V swing be enough to steer current into one side of a Diff pair?
 

Re: voltage doubler

The logic level voltage translator is very simple:

It has 2 NMOS. The gate of the second NMOS is driven by an inverter connected to the input. The inverter is connected to VDD1. The drains of the 2 NMOS feeding a cross-coupled PMOS pair. The cross-coupling mean connecting the gates and drains crosswise. The sources of the PMOS are connected to VDD2. Typical the drains of the PMOS are driving two inverters connected to VDD2. That supplies a complementary logic signal.

The PMOS dimension should be less strong than 2 times the NMOS to have sufficient speed. The exact dimension depend on the VDD1 to VDD2 situation.

The logic level voltage translator could translate up or down. Typical that is a stdcell or found as IOcell.
 
Re: voltage doubler


thanks for concern,,but could you upload the draw of the schematic?,,
thanks so much,,what is the upper limit for the operating frequency??

regards
 

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