Question about using non-overlapping clocks

non-overlapping clocks

I have a SC integrator implemented with complimentary switches. I use non-overlapping clocks. Does it matter if the complimentary clocks overlap.

What i mean is, the complimentary switch runs on two clocks that are the inverse to eachother. ie. Clock and then clockbar. So in an integrator there are two non-overlapping clocks and therefore with comp. switches two more clocks that are inverse to eachother. I cant get those two clocks to not overlap. Is this okay?

I hope i made sense here :?

Re: non-overlapping clocks

This is a bad idea.
You must be sure that there is non-overlapping clocks. that is to say,
there is a little interval between to clocks.
You can add some buffer for it

Re: non-overlapping clocks

I may not have been totally clear, i will try to explain again.

A complimentary switch runs off two clocks. One being the inverse of the other.

In my SC integrator i use complimentary switches for switching in the integrator.

I DO use non-overlapping clocks. However the INVERSE clocks i use for the switches do overlap. Is this normal?

Re: non-overlapping clocks

If the complimentary switch is the CMOS trans-gate, the gate signal of the nmos and that of pmos can be connected to the input and output of the inverter, respectively.

Re: non-overlapping clocks

Here is what I would do for non overlapping clock generator.

First, some defintions:

clock - (I hope this is obvious)

clock_A - this will drive any NMOS that are on when clock is high
n_clock_A - this will drive PMOS that are on when clock is high
clock_B - this will drive NMOS that are on when clock is low
n_clock_B - this will drive PMOS that are on when clock is low

There will be 3 additional signals needed:
n_clock - output of an inverter with inuput of clock
buff_clock_A - hopefully will become apparent
buff_clock_B - hopefully will become apparent

Now, the circuit. It will take 5 inverters and 2x2-input NOR gates.

INV0 input is clock, output is n_clock
INV1 input is clock_A and output is n_clock_A
INV2 input is n_clock_A and output is buff_clock_A
INV3 input is clock_B and output is n_clock_B
INV4 input is n_clock_B and output is buff_clock_B

NOR1 inputs are n_clock and buff_clock_B output is clock_A
NOR2 inputs are clock and buff_clock_A output is clock_B

In static conditions, clock_A, buff_clock_A and n_clock_B will be the same as clock, and n_clock, clock_B, buff_clock_B and n_clock_A will be complimentary to clock.

On transitons, the following sequences will occur:

clock H-L transition will drive n_clock L-H
n_clock L-H will drive clock_A H-L
clock_A H-L will drive n_clock_A L-H
n_clock_A L-H will drive buff_clock_A H-L
buff_clock_A H-L will drive clock_B L-H

I pause here, because this is key to the non-overlapping generation. clock_B going L-H needs BOTH clock H-L AND buff_clock_A H-L. Since buff_clock_A will not go L until AFTER clock_A has gone low and n_clock_A has gone high, this ensures that the clock A switches are OFF before the clock B switches get turned ON.

continuing where I left off:
clock_B L-H will drive n_clock_B H-L
n_clock_B H-L will drive buff_clock_B L-H

Now, this sets up for the non-overlap for the other phase. Since buff_clock_B is H, clock_A will remain low until buff_clock_B becomes low, which will be after the clock B switches are turned off.

Caution: do not put a buffer from the clock signals in this path to the switches. Such a buffer will no longer allow the circuit to be sure that the switches are OFF before turning the opposite phase switches ON.

Note: If your design requires events to occur in sequence for each phase of the clock, adding additional inverters in each chain (2 at a time...) will allow this. For example, buff_clock_A could be used to turn on an NMOS switch that needs to have a switch controlled by clock_A turned on first.

Re: non-overlapping clocks

Dear JPR,
It will be more clear and easier if u explain with a diagram..

Re: non-overlapping clocks

Much appreciate your effort in your reply JPR but that is a little confusing at first glance. Naisare is right, perhaps you have a diagram that could explain things a little clearer. Meanwhile i will try to decode what you have written

non-overlapping clocks

I guess when you say inverse clock overlap, you meant when the inverse clock signal goes high, there is an interval where both phase's inverse clocks are logic high. This is completely normal an actually it should happen this way, when the idea of non-overlapping is related to turning off the switches and the inverse clocks are used to control pmos transistors, which are off when the clock is high, with respect to the definition of the non-overlap clock they are still non overlap

Re: non-overlapping clocks

suppose you have non-overlap clock f1 and f2, driving NMOS switches, and also f1_bar and f2_bar, driving PMOS switches. f1 and f2 must be non-overlap (not both 1 at same time), and f1_bar and f2_bar must be inversely non-overlap (not both 0 at the same time). However, f1_bar is directly derived from f1 by just direct inversion, so f1 and f1_bar can overlap by its nature.

Re: non-overlapping clocks

Here is a diagram of what I described.