Question about using dual port BRAM with Spartan-II

Elephantus said:

Hi. If you are using RAMB4_S16 blockram from spartan II, you apparently cannot have the output in the same clock cycle the write enable strobe is asserted as the BRAM has a synchronous write, the ENA will get sampled on the next rising edge of clock.

Also, why do you need this? In a synchronous design, the data will get sampled on the next rising edge of clock on the other side, you simply need to delay the ENA signal for 1 clk period(provided that both sides are using the same clock speed).

I might be able to help more if you could post more about what are you trying to achieve.

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Elephantus said:

The PCI core therefore expects to have the data ready when the ENA signal which it produces is high, to sample it on the next rising edge of clock? This seems highly unusual for a synchronous design.
If it is absolutely necessary, you could either try inverting the port A clock, or use a 180deg phase shifted clock (respective to CLKA from your example),CLKA180, to clock the port A.
In that case, the ENA will be sampled in the BRAM on the rising edge of CLKA180, which corresponds to the falling edge of CLKA, and data will be present on the DOA output for the rising edge of CLKA.

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