question about two NMOS differential pairs and one PMOS differential pairs in my rail to rail input comparator？

Hi,

They are questions for the grown-ups but to fill in time until they arrive...

I'm not an IC designer, more of an ignoramus. I've seen op amp r2r with p and n pairs, I don't recollect seeing one with two n pairs. The p inputs are not visible in the partial schematic, I think.

BJTs may be used for (biasing and) temperature compensation. Shame emitter resistor values are missing. I assume they are there to balance nmos that with temperature rise turns on more, so bjts turn on more, so nmos (and obviously, cascode voltage rise with temperature rise also controlled this way) is turned off more, for a relative degree of temperature stability?

With so much missing from the incomplete schematic, ... bit of a guessing game.

Possibly, one n pair wasn't enough to modulate and if needed, cut out supply to pmos in cascode stage, so right-hand pair of n inputs finish the job off, or are just there to drain unwanted leakage voltages from next pmos pair in cascode?

But don't listen to me, I am really clueless about this kind of stuff.