Question about TSMC design rule.

[benny16]

tsmc 0.2um process

I read all the design rule but it do not mention the size of width (W), how to determinate it ?

Is it lambda=min length / 2, but why TSMC_0.35um lambda=0.2um, TSMC0.25um lambda=0.12um ? and what is the meaning of SCMOS ?

Thanks
benny16

 

[tok47]

w is normally depand on your design but the minimum is 0.35 for TSMC_0.35um

 

[benny16]

Thanks. That means
TSMC 0.25, W=0.25um;
TSMC 0.18, W=0.18um. Right ?

To more specific the width size, any equation can find the optimal width ?

benny16

 

[borodenkov]

I am not exactly sure, but I think that min transistor width in TSMC is not 0.18u, but a bit larger.. Min gate length is for sure 0.18u. Check the documentation in PDK

 

[Colbhaidh]

No !!

TSMC 0.25um means minimum L=0.25um not W. Min W is 0.36um
TSMC 0.25um means minimum L=0.18um not W. Min W is 0.27um

W is always larger than min L for a given technology due to short width effects (Vt roll off effects with W)