Question about the BJT models in CMOS process

[hyy95120]

Hi,
I have a question about BJT in CMOS process.
let's say, the foundry supplies model PNP18A100 for a 10ux10u BJT,

when i use it, do i need to put area parameter in the spice line?
such as,
Q1 1 2 3 pnp12a100 AREA=1e-10

or do i just use

Q1 1 2 3 pnp12a100
??
the reason why i am asking is that, the dc charactics are quite different by adding or not adding the area parameter.

I also noticed that after I did the layout extraction, the "area" parameters are added in the extracted netlist.

Please help!
Thanks a lot!

 

[leo_o2]

bjt post layout simulation

You don't need to add area.

 

[hyy95120]

post layout bandgap

but the question is, the extracted netlist from layout contains the area parameters and the post layout simulation is way off.

If I remove those "area" parameters from the extracted netlist, the results are good.

So, do you mean that the extracting software did a wrong job?

I've checked the calibre LVS script for both TSMC and SMIC, they all put "Area" parameters in the extracted netlist.

Do you mean they are all wrong and i have to manually remove the "Area" parameters from every extracted netlist?


Thanks!

 

[lylnk]

smic bjt model example

You should remove the "area".

You can read the pdf document in the folder of spice model.

 

[hyy95120]

bandgap bjt

Thanks a lot.

did a sanity check, and found adding "area" is giving unrealistic results.