Question about Synopsys dft OCC flow

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hgby2209

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1. If my design have PLL or clock divider or clock multiplier as my system clock source. Then I must use OCC flow? or normal flow is OK, too?

2. I had try the normal flow & OCC Flow for my design. But OCC Flow have following Warning :
Warning: Clock information for all sequential cells of design is missing. (TEST-374)

And the scan chain become very short !!!

Could anyone help me, thanks !!!
 

Hi,

For any flow, First make sure that your DFTC setup is clean.
Warning comes b'coz no testclk is created in DFTC script.

REgards,
Esh..
 

I want to know why TEST-374 exist and how to fix it.

I had tried the normal & OCC flow, both flow have many D1, D9, C16, S19 Warning. And I use autofix to fix.... but just OCC flow have TEST-374 Warning...
 

I had solved my problem....
I modified my pllclock point ....
move it before create_clock point then the problem fixed ....
 

Hello,

can anyone please provide a good document for studying OCC

Thanks and Regards
 

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