Question about sync FET conduction in synchronous buck

[analog_match]

In a synchronous buck when the sync FET conducts, the current will have to flow from gnd up to drain because the inductor current will flow in that direction. For this to happen the drain will have to be more negative than the source. Is this the correct explanation. I am usually used to seeing NMOS drain at higher potential than src and current flowing from drain to src.

 

[FvM]

Simply assume an almost constant Rdson for |Vds| << Vgs,threshold. The Vds polarity doesn't matter in this region.
For Vds < -0,5V, the substrate diode starts to conduct, of course.

 

[Mr.Cool]

you got it.

the trick is to know WHEN body diode starts to connect so that you can quickly turn ON your mosfet..

Mr.Cool

 

[analog_match]

I guess what y'all are saying is since the FET is in the linear region when on it behaves as a resistor and current flow can be in any direction. Thanks for help on this.

 

[eem2am]

No it is not in linear region.

The excellent sync buck is not that great because you have dead time for the fets...so when the series fet goes on, you will get a momentary large spike of current going through the shunt fet. -giving big switching loss for the shunt fet