Question about SS/TT/FF corner

[SJJJ]

First, I say sorry about my poor english, because my first language is not an english.
I can’t find perfect answer about my question so I come to this forum

MY Question is This.

I simulate in Virtuoso, for SS/TT /FF corner with CMOS Logic gates, inverter, nand, nor(which are made with NMOS and PMOS)

I expect that propagation delay of them are exactly same, like (FF is fastest, SS is slowest).

But some case, I found that it is not absolute. In some case, TT is faster than FF and moreover, SS is faster than FF

I guess that it because of capacitor between two NMOS which connected in serial(in NAND CASE)

but I can’t find what is the right answer, so I come to this forum to ask why propagation delay in SS corner is faster than FF corner
in somecase.

Thank you!

 

[ThisIsNotSam]

doesn't make any sense.

forget about nand and nor gate. just work with the inverter at first. the ss version should be the slowest, followed by TT and FF. make sure simulation scenario matches and is realistic: careful with ideal input transitions.

 

[SJJJ]

Oh, I Thanks a lot ! you mean the result that ss is faster than ff is not an exact result!! I'll try it again

 

[dick_freebird]

Be sure to look at loaded gates. A lonely gate with
thick gate ox and long channel "could" be "faster"
all by itself as its Miller capacitances are less and
maybe drive is better than proportionate. But hang
more load on it and the drive strength vs total
load becomes the dominant factor.

"Simulate it like you'll use it". Fanout <1 is useless,
fanout=1 is very limited usefulness (what, besides
delay lines / ring oscillators?).

If you dig deep maybe you will find the external
conditions that these corners were characterized
at.