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question about S/N of ADC

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uladz55

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It follows from Analog Devices bulletin that S/(N+D) is 89dB for 16-bit SAR ADC AD7686.
How is it possible?
 

The theoretical limit is 6.02x16+1.76=98.08 dB. A real ADC always presents a lower value. Why are you surprised ?
 

Hi,

I know this formula.
What does it mean - lower value?
Design must guarantee spec for any cases.

So, S/N >= 98dB ?
 

The difference between the two values is the important D in the first value which means distortion. There is evidently some significant nonlinearity in the converter.
 

the formula is for SNR wirhout considering the D--> distortion
That is only quantization noise is considered in that SNR equation..98dB.
Usually the practical value will be smaller. SNDR will be still smaller than SNR.
 

The formula I indicated is the Signal-to-noise ratio of an IDEAL ADC, due to the quantization noise. Real ADCs have, on top of that, more noise (thermal, flicker...) and also some distortion.

So, the ratio between the signal power and the power of everything else (quantization noise+other sources of noise+distortion) - SNDR is, of course, smaller.

It is even common to define a parameter called "Effective Number of Bits" (ENOB) as:

ENOB=(SNDR-1.76)/6.02

which basically tells you the number of bits that an IDEAL ADC would have, to have the same SNDR (in an ideal ADC SNR=SNDR). In this case you have ENOB=14 bit. This parameter gives a good indication of how far the real ADC is from the ideal case.

Regards
 

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