Jester
Full Member level 6
According to the old 1010.1 standard
"There are no CLEARANCE or CREEPAGE DISTANCE requirements for the interior of void-free moulded
parts, including the inner layers of multi-layer printed circuit boards."
Other references state 0.2mm or 0.25mm minimum
I have always taken a conservative approach and used 25mils minimum for <=300V, and never had an internal failure during Hi-Pot tests.
Yesterday I read this in an Infineon note about electrical safety and layout (section 4.2.11):
"Therefore, it is always suggested to keep the internal layers (separated just using few μm of prepreg) as common or ground layers which have a voltage drop not higher than 100V. Using higher voltage layers may be possible, but any overlap of inner layers must definitely be avoided."
This is the first time I have read about a 100V limit for layers insulated with prepreg, I assume they are concerned about voids in the Prepreg. I also read some specify a double layer of Prepreg to minimize the chance of a void.
Has anyone ever run into this 100V rule?
Comments welcome.
Link to paper: https://www.infineon.com/dgdl/Infin...N.pdf?fileId=db3a30433d1d0bbe013d20e0cbf017fe
"There are no CLEARANCE or CREEPAGE DISTANCE requirements for the interior of void-free moulded
parts, including the inner layers of multi-layer printed circuit boards."
Other references state 0.2mm or 0.25mm minimum
I have always taken a conservative approach and used 25mils minimum for <=300V, and never had an internal failure during Hi-Pot tests.
Yesterday I read this in an Infineon note about electrical safety and layout (section 4.2.11):
"Therefore, it is always suggested to keep the internal layers (separated just using few μm of prepreg) as common or ground layers which have a voltage drop not higher than 100V. Using higher voltage layers may be possible, but any overlap of inner layers must definitely be avoided."
This is the first time I have read about a 100V limit for layers insulated with prepreg, I assume they are concerned about voids in the Prepreg. I also read some specify a double layer of Prepreg to minimize the chance of a void.
Has anyone ever run into this 100V rule?
Comments welcome.
Link to paper: https://www.infineon.com/dgdl/Infin...N.pdf?fileId=db3a30433d1d0bbe013d20e0cbf017fe