Question about PLL VCO gain and the output frequency range

[Analog_starter]

bank of capacitors to tune vco

Hi all,

Is the VCO gain larger, the output jitter more serious?
If it is ture, we should reduce the gain to get better performance.
But if design the pll as a synthetizer, and it has a widely output
frequency range, for example, 100Mhz ~ 1000Mhz, the VCO gain
is very huge to meet the spec. How to solve this conflict?

Thanks.

Best Regards
Analog_starter

 

[khouly]

Re: About PLL vco gain

in some designs where the frequnecy range is very high , divide the range into more than one VCO , i have seen some chips divide the renge into 7 VCO's


wish this help

khouly

 

[gajen]

Re: About PLL vco gain

Differential architecture for PLL will help in reducing VCO gain by 2. In this control voltage will be differential, so for same power rail and same frequency range, control voltage will chnage will be double.

Other way is to have delay cell which changes by small amount over the whole control range but it will be tuned to different frequency ranges. So there will be 2 mode of tuning the delay. One by control voltage and other by a control bit deciding whihc frequency range you want to operate.

Third way is 2 minimze the corner variation of frequency change. Reduce temp/power supply dependency so that you have to operate over a smaller range.

 

[tfwee]

About PLL vco gain

Instead of design a high VCO gain that cover the whole frequency range, you may want to sub divide the whole frequency range into smaller frequency band. This way, you can design a small VCO gain. of course you need additional circuit to switch the VCO to different frequency in order to achieve a small VCO gain design.

 

[simonkuo]

Re: About PLL vco gain

Try to segment the VCO range. For instance, segment the VCO range to 4; 500M~1000M, 250M~500M, 125M~250, 62M~125M.
By the way, you can design a VCO range from 500MHz to 1GHz, then divide 2, 4 and 8 which is controlled by 2 bits.

 

[xwcwc1234]

Re: About PLL vco gain

To tfwee,
How to design a circuit to switch the VCO to different freq. ? For VCO frequency as high as 1GHz , is there any easy circuit to do that ?

 

[Analog_starter]

Re: About PLL vco gain

Thank you all.
I am still puzzled why the VCO gain larger, the output jitter more serious??
Who can show me more details?
Thanks a lot!

Best Regards
Analog_starter

 

[tfwee]

About PLL vco gain

To: xwcwc1234

For RF type of oscillator, you can design the VCO such that there is a bank of capacitors that allowed you to switch to different frequency band. By switching one bank, you can switch a fixed frequency. Whereas, there is another main tuning capacitor for your PLL to tune, which can be design a low KVCO gain. A good reference is a paper by A.A Abidi, "RF-CMOS Oscillators with switched Tuning", Custom IC Conf, 1998.

For ICO design, you can introduce a additional current steering method to increase or decrease a fixed amount of current to switch to different band in the ICO design.

Hope the above information help.