when I do at-speed DFT, I want to using the PLL output as refclk1 for launch and capture clock.
But there is a question, if the default PLL output clock frequency is not what I want. How can I make the PLL output clock turn to the right frequecy?
Use strap pin?
2. Can I config the PLL register to change the PLL frequency? I dont think so, but why?
Thanks, yes, there is OCC in my chip. Is there some other things to be done besides configuration PLL registers?
Due to the PLL needs some time to be stable after configuration, so what I should do in the ATPG patterns? waiting some cycle times ?
For that you need the documentation of PLL which is used in your design. yea we have to give some time to stable the required PLL output....yea..you have to wait for some cycles...
I think whn you config the PLL thn the PLL ip is in functional mode, thn by using the PLL lock and power down mode, you can switch to test mode (this information you can get from the PLL documentation)...
Yea if any strap pin is available thn we can use it....
BTW you can refer the testbench of PLL for just understanding how to work with PLL for particular frequency...