question about PLL divider value N > 2000

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tmchen00

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Dear all,

I need to use a PLL to generate a 25Mhz clock from reference clock 12KHz.
But I have no idea if the feedback divider values N has any limit. Is the values
(>2000) reasonable?

Thanks.
TM
 

It is very reasonable, for example the GSM frequency synthesizer generates 900MHz from a reference frequency equal to 200KHz, i.e. the division ration is within the 4000 range
 

The only problem you may have is the phase noise: the loop transfer of function of most noise sources in PLL is proportional to N. But N=2000 is not high value.
 

To generate the 25MHz Frequency, why not try to use the pre-divider divide by 11,
and the loop-divider divide by 23?
By the way, the output frequency will be
12MHz X 23 /11 ≈25MHz
 

The other method is two loop pll, this is to say, first is 40 times, the second is 50 times.
This method can be small noise and quickly respond.
 

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