Question about output resistance in opamp and bias current

[Analog_IC]

why???

Q1. To achieve highe gain in voltage amplifer output resistance is increased.
And increasing output resistance may seem to make the speed of circuit quite
susceptible to the load capacitance. why???

Q2. Total bias current in folded cascode case is required higher than in simple cascode stage to achieve same performance. why???

 

[flatulent]

Re: why???

On question 1, the equivalent current source of the transistor model is driving a resistor in parallel with a capacitor. Transform the current source and the parallel resistor into an equivalent voltage source in series with the resistor. Then the capacitor forms a low pass RC network for the signal to pass through. This limits the frequency response. For larger resistor values the capacitance makes a lower frequency low pass filter.

 

[tia_design]

Re: why???

Take diff pair for example, generally, its gain is Gm*Rout, so the higher the output resistance, the higher the gain. And output node is dominant pole, it is 1/(Rout*(Cout+CL)), you can see, when load capacitance is increased, the time constant is increased, which means the bandwidth is decreased.

 

[srivatsan]

Re: why???

Q2:
Ans: With regard to the Fig 6.1-9 in CMOS Analog Circuit Design (Allen and Holberg), it is very clear the instead of two branches of MOS in cascode configuration, in folded - cascode you have two more branches to support the "non - folded"part of the folded cascode , ie, usually the input transistors. Hence the current increases (in totality).

Hope this clears up the problem.

Srivats