Question about optimizing delay in NAND gate

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42) Let A and B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the output?

The answer is the A shud be placed closer to output but why ??
 

Re: NAND GATE

Dear dude,

As in NAND gate since NMOS are connected in seies, And A is connected near the output

Consider B turns ON first, the VSS connected to the source now will pass through

B connected NMOS fine,

But to obtain the output as '0' A has to be turned ON then only we get output as '0'.

Hence the NMOS connected to A has to turned on first then to turn on B. then only we get an output '0' with less dealy or No delay

Hope u got

phutane
 
Re: NAND GATE

consider this.... if B is nearer the load then while turning on it would have to drive the capacitance of A as well as load....
if A is nearer the load then consider the case that it is on but B is off since its input hasnt arrived yet but when it arrives it has to carry charge from the supply all the way to the load through A.....
 

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