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Voltage headroom basically refer to the margin on which your circuit can be biased and the output swing is depend on that as well. Let say you design a simple common source amplifier with a 1.8V supply voltage, the max you can stack a transistor could be 2 to 4 which include the load as well. So, when you add more transistors, you will face problem in keeping them below supply voltage and the upper transistors won't be in saturation and also when it comes to biasing the gate of each of them,the problem will be there.
Simply, voltage headroom means limitation from the power supply voltage and the situation in where you couldn't add/stack more transistors in series (where the Drain voltage of the most upper transistor exceeding the power supply) and until the condition for them to be in saturation is aborted.
Hi,suria3
I also understande the voltage headroom is critical limitation in the design of LV analog cicuirts, and this implies growing circuits horizontally instead of vertically is preferred. But I want to know the exact quantitative relation, if there is, of a given schematic. Let's say, for a common-source amplifier with PMOS current source load, the supply voltage VDD, input DC bias VCM, and PMOS gate bias Vp, what about the headroom? Thanks!
Regarding your question, I don't have exact circuit to use in explaning to you. But according to the situation you described, i can see that there is no headroom limitation in this case due to just two MOS which have good headroom. For a VDD that is far above the saturation level of the PMOS current source, the common sourse amplifier can work optimumly. Now, the problem will arise if you cascode the common source until the top transistors couldn't be biased due the increase in the number of Vtp and also margin of the top transistors to be in saturation is limited. Another example is when you design a differential amplifier like Cherry Hopper with lower voltage supply, u will face this headroom voltage limitation when it comes to stack up a few transistors, which will definitely force the tail transistors to fall in triode region due limited supply voltage and the output swing also had to be limited.
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