Buriedcode
Full Member level 6
Hi,
I'm writing a multi-level code (well, just the top level and 5 lower ones) and I have a problem. First of all a simple question:
In ABEL (not veri or VHDL) can an internal connection be made between two lower level modules without routing them through the top level? I believe the the term 'wire' is used in verilog to describe such a structure.
By the way, I don't know VHDL or Verilog at all 8O
The reason I ask is because, one of my lower level modules is an 8-bit shift register, the parallel output of which, is interfaced with the top-level module and connected to 8 pin's on the CPLD. This 8-bit number must be read back by a different sub-module. You may be wondering what is wrong with doing it this way....well...
Looking in the constraints editor (I'm using ISPlever) the 8-bit number, called 'd7..d0' appears 3 times. Once for the Pins (output) and twice as NODES (Od7...Od0, and, Id7..Id0). This means that these 8 bits use 24 macrocells. <--- 8 too many
If anyone could provide a solution to this I would be very grateful, its been bugging me for a while now, and I really don't have a clue. :?:
I don't want to have to get a larger PLD.
When I was designing it I 'assumed' that the 8 bits would be assigned to pins and then other modules could read off from these 8 pin's meaning only 8 registers are used.
Thankyou.
I'm writing a multi-level code (well, just the top level and 5 lower ones) and I have a problem. First of all a simple question:
In ABEL (not veri or VHDL) can an internal connection be made between two lower level modules without routing them through the top level? I believe the the term 'wire' is used in verilog to describe such a structure.
By the way, I don't know VHDL or Verilog at all 8O
The reason I ask is because, one of my lower level modules is an 8-bit shift register, the parallel output of which, is interfaced with the top-level module and connected to 8 pin's on the CPLD. This 8-bit number must be read back by a different sub-module. You may be wondering what is wrong with doing it this way....well...
Looking in the constraints editor (I'm using ISPlever) the 8-bit number, called 'd7..d0' appears 3 times. Once for the Pins (output) and twice as NODES (Od7...Od0, and, Id7..Id0). This means that these 8 bits use 24 macrocells. <--- 8 too many
If anyone could provide a solution to this I would be very grateful, its been bugging me for a while now, and I really don't have a clue. :?:
I don't want to have to get a larger PLD.
When I was designing it I 'assumed' that the 8 bits would be assigned to pins and then other modules could read off from these 8 pin's meaning only 8 registers are used.
Thankyou.