Question about Mixed verilog/vhdl simulation in NCsim

nasimz · Jun 7, 2011

Hello,

I am using a verilog testbench, but it includes instantiations and parameters defined in vhd files.
I compile those files with ncvhdl to a library . How can I give the path of this library to ncvlog to use it for compiling the testbench?

best,
nasim

ljxpjpjljx · Jun 8, 2011

you should have a wrapper for vhdl model and instance in in the testbench!

nsingh95 · Jun 10, 2011

Hi nasim,
Just try to remember one thing. In testbench there may be modules of both vhdl and verilog.
When your testbench is verilog then whille creating instance make all the instance in verilog even the vhdl file.
Similarly for vhdl testbench.

I think ur problem is solved.

regards,
Nishi.

Question about Mixed verilog/vhdl simulation in NCsim

nasimz

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ljxpjpjljx

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nsingh95

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Question about Mixed verilog/vhdl simulation in NCsim

nasimz

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ljxpjpjljx

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nsingh95

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