question about mixed signal simulation using cadence

[lily1981216]

Hi, everyone, I put my circuit (digital and analog )in one config. When I simulate it ,I meet with a strange thing. The output is only right when the input is 001. I don't why? I would be a break down. I hope anyone could help me! Thanks very much! The circuit figure is in the attachment.
code

module decoder3_8(c2,c1,c0,d5,d4,d3,d2,d1,d0);

input c2,c1,c0;
output d5,d4,d3,d2,d1,d0;
reg d5,d4,d3,d2,d1,d0;

always @(c2 or c1 or c0)
case({c2,c1,c0})
110:{d5,d4,d3,d2,d1,d0}=11_1111;
101:{d5,d4,d3,d2,d1,d0}=01_1111;
100:{d5,d4,d3,d2,d1,d0}=00_1111;
011:{d5,d4,d3,d2,d1,d0}=00_0111;
010:{d5,d4,d3,d2,d1,d0}=00_0011;
001:{d5,d4,d3,d2,d1,d0}=00_0001;
default: {d5,d4,d3,d2,d1,d0}=6'bx;
endcase
endmodule

 

[JoannesPaulus]

what happens in the other cases?

 

[lily1981216]

what happens in the other cases?

All of the output is "0" in other cases. All the circuits is in the config. The simulater is spectreverilog. The interface library has been intialized.Thank!

Added after 2 hours:

Hi, everyone, the problem has been solved and there is something wrong with the code. Somebody helps me to modify that. Thanks to everyone!!!