Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Question about mdac settling time in pipeline ADC

Status
Not open for further replies.

ljy4468

Full Member level 4
Full Member level 4
Joined
Jul 20, 2005
Messages
232
Helped
13
Reputation
26
Reaction score
1
Trophy points
1,298
Location
South Korea
Activity points
3,023
hi everybody?
I've question about mdac settling time in pipeline adc

Assume, Clock speed is 80Mhz,
(half of the T : 6.25ns)

Then, my mdac settles in about 6.25ns???
Or 4 or 5ns????

Thanks in advance.
 

Re: mdac settling time

You need to understand and clearly define what is the real meaning of 'settle': it is the accuracy that the MDAC needs to achieve, which depends on the overall accuracy of the pipeline ADC, if the MDAC is the first stage of such a pipeline.

A normal way to specify this is to settle within N-bit accuracy over half of your clock rate (slightly less than half due to non-overlap overhead).
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top