Question about MDAC and multiple stages

[SteS]

Hello,
I am working on a MDAC for a pipeline ADC.

The attached schematic is an example of a single stage from which I removed the switches of the "DAC" part, so it should just multiply the signal. Let's ignore the offset for now.
In the first phase the switches are in the dashed position and Vin is sampled on C1+C2. The total charge is Q1 = Vin*(C1+C2).
In the second phase the switches are in the solid position: C2 is connected to Vout an C1 is connected to ground. The total charge is now Q2 = Vout*C2.
By equating the charges from phase 1 and phase 2, we get a gain Vo/Vi = (C1+C2)/C2. Is the analysis correct until now?

My question is: what happens when an identical stage is connected to the output with inverted phases (when stage 1 is in phase 2, stage 2 is in phase 1)?
In that specific case, we would have the sampling capacitors C3+C4 of the following stage connected between Vout and the virtual ground. But C2 is also connected between Vout and virtual ground, so they are in parallel.
Will the gain become Vo/Vi = (C1+C2)/(C2+C3+C4)? If not, why does the load not affect the gain?

I got this question because in most papers and books I looked at, no one mentions buffers between stages in pipeline ADCs.

EDIT: I came to the conclusion that in the second phase the charge at the negative input of the amplifier cannot change, and it is that charge that sets the voltage across C2, regardless of what's connected to the output. It is the amplifier that provides enough current to also charge C3+C4. Is this correct?

Thanks in advance.

 

[sidun.av]

Hi @SteS ,

Is the analysis correct until now?

Your analysis for a 1.5-bit flip-around MDAC is correct.

Answering your question, I think that the main confusion here is that you are trying to equalise two separate virtual grounds which is not correct in my opinion. That said, 1st stage opamp cannot affect the virtual ground of the 2nd one even though they are both called "ground". So, 1st stage opamp will try to force its Vout1 to be so that its negative input is 0. C3 and C4 will work here only as a load without affecting the gain of the 1st stage.
Thus, the 1st stage opamp should have enough BW (output current should be high enough) to charge C3 and C4 before the amplification phase of your 2nd stage begins. In real pipeline ADC designs a stage scaling is usually used, so the 2nd stage capacitors are at least 2 times smaller than the 1st one which should relax 1st opamp requirements.

P.S. This book is very useful, I definitely recommend:
https://link.springer.com/book/10.1007/978-90-481-8652-5

Hopefully, that helps.

 

[SteS]

Thank you for your answer and the bok recommendation, I'll give it a look!