Question about manual fix timing violation in SOC encounter

[llbaobao]

Can someone tell me some ways that can be used to manual fix the timing violation in SOC encounter?

Now I did a case about 100MHz, Now there is about a timing slack about 0 ~ -1.8ns
for about 40 reg2reg paths. Other paths are already ok.

I let the tool itself to fix the timing violation, mainly use "optDesign" and its incremental action to fix timing violation, but after many turns running, there is no change in timing violation.

Can someone tell me how to manual fix the timing violation in it?
I have no idea on how to manual fix the timing violation in SOC encounter.
Thanks!

 

[cop02ia]

Re: Question about manual fix timing violation in SOC encoun

Hi,

My 2 cents worth:
1) Browse details of violating paths, & use ECO to fix by upsizing or downsizing cells which seem to be contributing to significantly large timing delays.
2) If the paths are long, do ECO to plug in buffers/inverters.

Remember to ask the darn tool to do Refine Placement everytime lest you get overlapping cells.
As usual, *some* iteration may be needed.

Best regards.

 

[llbaobao]

Thank you for your reply!

Can you give me a example to give me a more detailed explain? thanks !

 

[kumar_eee]

@cop02ia, Thanks alot for the info!.

 

[zhangdengjun010]

very good, how to run ECO,can you give me a sample scritp or example, thank you!