Question about LDO on chip?

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letan

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When I use a LDO, I need a capacitor at output(microfarad). But, if I design a LDO on chip to supply voltage for some blocks on chip, how must I do to decrease capacitor at output ( total capacitor on chip 1nF) . Please help me.
Thanks.
 

as i know ,this time ,you can add pin at the ouput of LDO, so that the big cap can be out chip

letan said:
When I use a LDO, I need a capacitor at output(microfarad). But, if I design a LDO on chip to supply voltage for some blocks on chip, how must I do to decrease capacitor at output ( total capacitor on chip 1nF) . Please help me.
Thanks.
Click to expand...
 

agree, most likely, there must a off chip cap @ PAD and yr LDO will connect with pad. Also, the loading current will large( in terms of mA).......it seems this may be a too large current flow in yr chip internally....

if a device is need to provide stable Vo to internal blocks, LDO ....i guess may not the best approach since, may be just a two stage AMP(from alogrithm point of view, similiar to LDO) can do so......this is what i guess...
 

letan said:
When I use a LDO, I need a capacitor at output(microfarad). But, if I design a LDO on chip to supply voltage for some blocks on chip, how must I do to decrease capacitor at output ( total capacitor on chip 1nF) . Please help me.
Thanks.
Click to expand...

you can try the architecture without external capacity. it has internal frequency compensation.

regards
 

hi all,

most likely, there must a off chip cap @ PAD and yr LDO will connect with

pad. Also, the loading current will large( in terms of mA).......it seems this may be a too large current flow in your chip internally....


if a device is need to provide stable Vo to internal blocks, LDO ....i guess may not

the best approach since, may be just a two stage AMP(from alogrithm point of view, similiar to LDO) can do

thanx......
 

Hi,

If the load regulation spec of the LDO is not very tight (few 100mV drop is allowed) I mean it is used for a digital supply then you can use a NMOS type source follower stage which does not make the output node dominant pole and hence you can have the gate as dominant pole ( by few tens of pF cap)and you need not have an off chip cap.

If you need a high regulation, then I guess you NEED an off chip cap.

Regards,
Jitendra Dhasmana.
 

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