Question about ISE processes: Synthesize, Translate, Map...

ISE process question?

Hello all,

I have used ISE for about 1 week, and have 2 question:

1) What's the difference with "Synthesizer" and "Translate"
2) What's the difference with "Map" and "Trace and Route"

In my view, the first two all translate RTL to primitives, and the second two Map the primitives to Slice, is that right?

Regards,

Davy Zhu

Re: ISE process question?

You will find all what you want to know in the Development System
Reference Guide coming with the ISE

ISE process question?

Well, but I haven't that Guide.

ISE process question?

i think here u'll find the answer:

**broken link removed**

ISE process question?

Synthesize mean the process you convert your hdl code into RTL netlist. Translate mean the process you convert your RTL netlist into gate level netlist. From here, Fitting mean the process of ISE place your gate level netlist into CPLD; Place and Route is the term used by FPGA for fitting process.

Re: ISE process question?

The synthesis process will check code syntax, and analyze the hierarchy of your design. These processes will ensure your design is optimized for the design architecture you have selected. Your HDL code description CAN be transformed into a digital circuit that may or may not be functional or could be simply junk, however, the code is written as such to create digital schematic or black box from it. If the code is not synthesizable it is grossly erroneous.

Translation comes after synthesis, it involves conversion to technology library parts. Translate is the first step in the implementation process. The Translate process merges all of the input netlists and design constraint information and outputs a Xilinx NGD (Native Generic Database) file. The output NGD file can then be mapped to the targeted device family.

The Map process creates an NCD file. The NCD file will be used by the PAR process for further processing.

You can run the place and route (PAR) process after you have mapped your design. PAR uses the NCD file created by the Map process to place and route your design.

This is more or less the process with almost all FPGA vendors.