Leo@27
Newbie
I'm wondering if there exists a way other than the traditional Miller compensation to compensate a classAB output stage opamp.
I ask this because when driving a large capacitive load, the capacitance used for compensation also increases and is very difficult to integrate it on chip. I need the classAB to provide rail-to-rail output range, and the gain of the second stage op-amp is sufficient for my design, but the capacitive load requirement makes traditional on-chip compensation unusable.
Here's my question: what frequency compensation architecture is typically used when driving an 100s nF- or even uF-rated capacitor? Is it possible that a 3-stage op amp is more viable in this case, as opposed to a 2-stage op amp? Could anyone answer my question please?
I ask this because when driving a large capacitive load, the capacitance used for compensation also increases and is very difficult to integrate it on chip. I need the classAB to provide rail-to-rail output range, and the gain of the second stage op-amp is sufficient for my design, but the capacitive load requirement makes traditional on-chip compensation unusable.
Here's my question: what frequency compensation architecture is typically used when driving an 100s nF- or even uF-rated capacitor? Is it possible that a 3-stage op amp is more viable in this case, as opposed to a 2-stage op amp? Could anyone answer my question please?