question about dual-slope integrated AD converter

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mosis

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i need a dual-slope integrated AD converter with specs as below:
1) speed: about 10~1k sp/s
2) ENOB: 16 ( >12 is must)
3) Power supply: 3V
4) INL: ±1LSB
5) DNL: ±1LSB
6) SNR: >55dB
7) Power Dissipation: <2mA
and i use o.35um TSMC CMOS process
who can give me some advice or papers about it?
many thanks!

mosis
 

To my knowledge, dual slope AD convertors are slow. Maybe upto 25 samples/s.
 

just as you said the dual-slope AD is slow.
for a 2bit ADC, the speed =fCLOCK/2³.to design a 10bit 1ksps/s ADC, we need a
clock source about f=1k×2048=2MHz! And the main issue for designing a socalled
"high-speed" dual-slope ADC is to design a high-speed, high-accuracy comparator and integrater. Besides, there comes another question: how to solve "over-integrating"when the input analog signal is close to the Vref(full scale of integrater), due to the charcteristics of integrater, it may takes a long time.
 

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