Question about current steering DAC

[colinwang]

Hi all,
I've designed a 10bit 100M current steering DAC. The simulation results using ideal voltage supply is good. But when i add simplified bond wire model(2nH inductor + 0.5Ohm resistor) on the VDD and GND. The output is totally wrong and there is a large oscillition. I add a decoupling capacitor between analog vdd and gnd, there is no obvious effect.
Could anyone tell me how to deal with this problem? Thanks very much!

 

[wifish2009]

Hi all,
I've designed a 10bit 100M current steering DAC. The simulation results using ideal voltage supply is good. But when i add simplified bond wire model(2nH inductor + 0.5Ohm resistor) on the VDD and GND. The output is totally wrong and there is a large oscillition. I add a decoupling capacitor between analog vdd and gnd, there is no obvious effect.
Could anyone tell me how to deal with this problem? Thanks very much!

hi colinwang

when you add simplified bond wire model on the VDD and GND, you can observe the reference voltage .

 

[colinwang]

Thank you very much!
I seperate the supply of digital part, latch switch and current source. Due to the parasitic capacitance, the reference vdd and gnd are interferenced during the switching time. So there is no quiet place in the chip. The changing current on the inductors makes the output oscillation and needs a relatively long time to settle. How to solve this problem? Thanks!

 

[colinwang]

I found that the bond wire and lead inductance on the output has significant consequence. The output oscillation occurs every clock cycle. It's especially critical when the speed is high. Before it settles, the next clock comes. I add a small resistor to attenuate the oscillation. However, there is no obvious effect. how to deal with this problem? Thank you all!