Newyoo
Newbie
Hi,
I build a tiny 180nm SRAM macro and am trying to generate a lib file using primelib.
However, I encountered some issues.
In the characterization flow, the tool will generate a lot of timing arcs corresponding to the inst. file automatically.
I checked the arcs, all are necessary for lib generation. But, there are some errors in the initialization__ACQ__*.initialization files.
For instance, in my designs, there are two timing arcs:
(1) capload0__delay__CLK__lh__DO__lh__ACQ_1 (correct)
in the deck file, this tb includes the init. file (......../initialization__ACQ_5.op_cond_all.initialization).
I checked the init_5. file, the configurations of node set are correct. the DO signal's initial level is 0. Once clk rises, the DO can output 1 based on the SRAM bitcell' level, which is 1.
So, I can observe the DO_l-to-h waveform.
(2) capload0__delay__CLK__lh__DO__hl__ACQ_1 (wrong)
in the deck file, this tb includes the init. file (......../initialization__ACQ_4.op_cond_all.initialization).
I checked the init_4. file, the configurations of node set are wrong. the DO signal's initial level is 0. However, it should be level 1.
So, I cannot observe the DO__h-to-l waveform.
I am wondering if I can configure the nodes' initlization state file manually using some commands. The tool seems to have some issues about this part.
thanks.
I build a tiny 180nm SRAM macro and am trying to generate a lib file using primelib.
However, I encountered some issues.
In the characterization flow, the tool will generate a lot of timing arcs corresponding to the inst. file automatically.
I checked the arcs, all are necessary for lib generation. But, there are some errors in the initialization__ACQ__*.initialization files.
For instance, in my designs, there are two timing arcs:
(1) capload0__delay__CLK__lh__DO__lh__ACQ_1 (correct)
in the deck file, this tb includes the init. file (......../initialization__ACQ_5.op_cond_all.initialization).
I checked the init_5. file, the configurations of node set are correct. the DO signal's initial level is 0. Once clk rises, the DO can output 1 based on the SRAM bitcell' level, which is 1.
So, I can observe the DO_l-to-h waveform.
(2) capload0__delay__CLK__lh__DO__hl__ACQ_1 (wrong)
in the deck file, this tb includes the init. file (......../initialization__ACQ_4.op_cond_all.initialization).
I checked the init_4. file, the configurations of node set are wrong. the DO signal's initial level is 0. However, it should be level 1.
So, I cannot observe the DO__h-to-l waveform.
I am wondering if I can configure the nodes' initlization state file manually using some commands. The tool seems to have some issues about this part.
thanks.