Question about clock domain synchronous

[EDA_hg81]

I have a master clock 4MHZ and another clock 200KHZ generated by master clock.

At the beginning, Master clock domain will enable 200KHZ clock domain by latching an enable signal “eni2c”. If the 200KHZ clock domain received “eni2c” signal, 200KHZ domain will finish programming EEPROM, after that 200KHZ will latch a signal”i2cdone” to trigger master clock domain i2c programming is done.

When master clock domain received the signal “i2cdone”, it will lower “eni2c” signal therefore 200KHZ clock domain will be disabled.

In my mind, the signals “i2cdone” and “eni2c” can be received reliable by two clock domains.

But when I used scope to check, 200KHZ domain block is not trigged sometime.

What is the reason for this?

Thank you for you any suggestions.

 

[maheshkuruganti]

Maybe you should try a Post Place and Route Simulation with something like ISE Simulator. I had the same problem with a Pulse Generator and after running Post Place and Route. I found sometimes the setup time may not be enough. So Try it and Good Luck.

Added after 40 seconds:

Also ppl can help better if you give the code.

 

[EDA_hg81]

Thank you so much.

I will try it and I am using Quartus II.

Added after 2 minutes:

If you want the code, Please let me know your Email address.

I have used Quartus to simulate, the simulations are good.