Question about Clock and Data Recovery,thanks.

[swicap]

for CDRs employing linear or bangbang PD,
what is there capture range ?

will cdr lose lock if large jitter appear in input data?
then what kind of jitter is more harmful? DJ or random jitter?

Is there possible method to design a robust lock in detect circuits to judge cdr in
lock or not?

Thanks.

 

[MSSN]

for CDRs employing linear or bangbang PD,
what is there capture range ?

will cdr lose lock if large jitter appear in input data?
then what kind of jitter is more harmful? DJ or random jitter?

Is there possible method to design a robust lock in detect circuits to judge cdr in
lock or not?

Thanks.

Normally, CDRs have limited capture range and needs a helping loop during acquisition.

Yes, there is a possible method to design a robust lock detect circuits that detects cdr locking and unlocking to a reference frequency within a predefined ppm error.

Check Razavi's book , Design of Integrated Circuits for Optical Communications, it has a complete chapter on CDRs

 

[swicap]

hi,MSSN,thanks for reply.
I just want to know exactly the deviation of frequcy that cdr can capture with pd alone.
I have read razavi's book already.
It doesn't descript circuit implementation on
CDR lock in detector design, I think.
Woule u give more details? Thank u.

 

[beckchm]

jitter is large

range cannot cover the change