Question about clearance from DNW to N+ diffusion which is outside NW

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littlej_zju

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From the design rule, there is minimum clearance requirement from DNW to N+ diffusion which is outside NW. And, DNW cut N+ diffusion outside NW is not allowed.
Foundry said that "if half of N+OD with PW --> ( N+/PW ) NP diode, Half of N+OD with PW +DNW --> (N+/PW/DNW) NPN bipolar, It may has leakage or some unexpected issue". But, I can't image which leakage would happen.
 

Both N+ contacts (outside of) & (cutting) DNW - together with the p- substrate and the N+ DNW tap - form a parasitic npn BJT. Should the two N+ taps (collector and emitter of the npn) be on different potential, a β-magnified collector current would flow. Min. G separation ensures sufficiently low β.

The parasitic npn BJT forming of the DNW cutting N+ contact isn't easily to be seen, but one shouldn't forget that the DNW doping at the surface is rather low, hence a large resistance between the two N+ contacts could exist, depending on their separation.

Foundries simply won't risk too high a leakage current, so they don't allow such alignment generally.
 
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