The time constant of the RC is 5 us and your signal period is 2% of this so there will be little pulse distortion. The average signal on the right is the power supply voltage. The AC component of the input gets put across the capacitor so you will get on the transistor side the same shaped waveform but with the high Vcc+0.1 and the low Vcc-0.1.
hi flatulent, tat's wat i tot too.... the waveform should be at (vcc+0.1) as high and (vcc-0.1) as low... but instead i got (vcc+0.2) as high and vcc as low... any explanation for that?
The circuit is linear so superposition holds. There is an AC and a DC component. On the right the DC component is the power supply through the resistor with no current flowing. The AC component gets across the capacitor.
This is the verbal solution. You can also do the math.
Yes, all of this assuming that the FET does not have protection diodes on the gate and the gate capacitance is very small compared to the 100 nF. Also that the input pulse is periodic (you mention a repetition rate of 10 MHz.) A one time pulse would get you the vcc, vcc+0.2 situation.
I think it should be vcc+0.2 and vcc for the high and low value. since after the positive pulse, the AC part will stay at about 0.2 (since 0.1u <<5u) and when the negative pulse comes, the AC part goes to 0.
When there are 0.2v difference between the high and low level of pulse (no matter from 0 to 0.2 or from -0.1 - 0.1), the right side of Cap will go up as high as 0.2V and then start to discharge, however, since the time constant of the RC high-pass filter is much larger than signal's period, the voltage will not go down a lot (or it approximately stay at 0.2V), and then a negative pulse will bring it to 0V.....