Binome
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Hi,
when simulating my design with no optimization I can see one of the output signals changing from 0 to 1 then back to 0. When simulating with optimization this signal is deleted and I don't understand why. Is there a way to know? (An ISE synthesis doesn't show any error or warning. I can't publish my vhdl code because it's too long and because of property.)
Thanks for any help.
when simulating my design with no optimization I can see one of the output signals changing from 0 to 1 then back to 0. When simulating with optimization this signal is deleted and I don't understand why. Is there a way to know? (An ISE synthesis doesn't show any error or warning. I can't publish my vhdl code because it's too long and because of property.)
Thanks for any help.