anumna33m
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Hey
I have designed a median filter in FPGA using verilog. I have given the input in this programs using readmemh command in test bench. The problem is that For my input A,B,C,if i want to assign A=first value B=3rd value n C = 7th its giving xxxxx in output thus its unable to read unsequential data from my input file .
Please Help
Regards
I have designed a median filter in FPGA using verilog. I have given the input in this programs using readmemh command in test bench. The problem is that For my input A,B,C,if i want to assign A=first value B=3rd value n C = 7th its giving xxxxx in output thus its unable to read unsequential data from my input file .
Please Help
Regards