Query regarding a verilog statement

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mjuneja

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What does this statement means ??

Code Verilog - [expand]
1

assign a = ((1'b0) != b);
 

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Assigning a test for b variable bit 0 != 1 .....?

From manual an example of typing -




Regards, Dana.
 

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mjuneja said:
assign a = ((1'b0) != b);

What does this statement means ??
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I'd be more inclined to say this means the person who wrote the code doesn't know what they are doing.
Or they were lazy and did a global replace of a signal with (1'b0), instead of just assigning the signal with 1'b0 and letting synthesis deal with the logic optimization.
 

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this might be automatically generated code. that would explain why such simple logic became a not so readable statement.
 

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