Query of inut offset voltage of two stage op-amp

systematic offset sigma

I have some query!
I have done simulation of two stage CMOS op-amp for input offset voltage. My op-amp is PMOS input diff pair.
What I did is that, I connected one input negative terminal to output. Now at second positive input terminal I applied a dc voltage of 1V. My Vdd is 3.3 V.
Now from ADE I click on, I min dc op point , then went to setup, then calculator, from calculator I chose dc then go to schematic and did Input +ve terminal Minus(-) -Ve input terminal.
Now I get the expression of Voffset in ADE and run the simulation.My typical Voffset is in range of 3 to 4 µV.
Now I chose the Monte Carlo simulation parameters of process and mismatch and run Monte Carlo Simulation for 1000 run and plot the histogram. It gives the mean value is 17.02 µV and standard Deviation is 892 µV.
now my question is
1. Is my procedure to simulate the offset voltage is right
2. is SD= 892 µv my Voffset value
3. If yes how itis possible to have mean value less than standard deviation.
Can someone help regarding to my query.
with regards
Thanks in advance and waiting for response
Kapil

2 stage op-amp

can u post the diagram

two stage opamp

That means that you have a systematic offset of 17µV and a random offset with a 3 sigma of 2.676mV (3 times your sigma).

That sounds too small for systematic, but if you say you have it, fine with me. The random part is totally normal. 3mv makes sense.

two-stage op amplifier design

1) Your procedure is correct. Here you can simulate offset at edge values of supply voltage and ICMR voltage, temperature (cold,normal,hot).
2) SD=892uV is standart deviation. If you design for 3 sigma your offset voltage is in range +/-2.676mV within 99.97% yield.
3) Mean value or systematic offset is caused by finite gain of amplifier (more gain -> less offset). In amplifier is designed correct its systematic offset is lower than random offset.