QUery in transition delay after clock tree synthesis

nathanpk · Aug 8, 2013

Query in transition delay after clock tree synthesis

Hi,

I am new to physical IC design and I am working on CTS now. After CTS when I checked the clock transition time, it seems that rise transition time is different from fall transition time. Can anyone tell me why its different?

Thanks!

AdvaRes · Aug 9, 2013

use synopsys tool use the set_clock_transistion command.
For more detail see: Milkyway and Physical Implementation Commands p 571.
www.61eda.com/code/attachment.php?aid=3438&k...t=1287224009

mail4idle2 · Aug 15, 2013

Rise and fall time of any cell is not same. that the reason we develop clock cells separately which gives almost same rise and fall time

QUery in transition delay after clock tree synthesis

nathanpk

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AdvaRes

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mail4idle2

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QUery in transition delay after clock tree synthesis

nathanpk

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