Query for test pattern generation

When a chip is fabricated it goes for testing if different faults like stuck at faults. Why do we then go for ATPG? The ATPG is not on silicon. What is tested in ATPG?
Which tool of Synopsys and Cadence is used for ATPG?

Synopsys has two tools, one is dft compiler and the other is tetramax. What do these two different tools do for testing? I think dft compiler is inside Design compiler and it is ised along with synthesis. Is not it?

We do ATPG to generate the patterns which will identify faults like stuck-at, propogation .. Normally we take a post-synthesized netlist and give it to a ATPG tool. ATPG tool will identify possible faults for each nodes of combinational logic and flops and generate patter list file along with testbench. Using testbench and pattrn file, we simulate post-synthesize netlist with and without SDF. Once SDF is timing met and simulation passes with SDF with timingcheck, that netlist will go to foundary for further processing and will finally be resulted in CHIP. Post-synthesized netlist can be considered as softcopy of actually CHIP. Once we have CHIP ready, ATE team will apply the saved pattern file and test the chip. If chips pass the test, it will go to market.

synopsys's Design compiler is used to insert scan and other process in to netlist while tetramax is used for pattern generation.

Cadence have Enconter test for pattern generation.

to facilitate the chip testability, the scan is inserted by two (three) phases:
1- DFT tools are used to check the scannability and to insert the scan elements & connections.
2- DFT advisor for example, could give some advice(s), for example where it could be interesting to add some test-points (added scan-flop used only in scan mode).
3- ATPG tools generate the patterns (transition-stuck-iddq-bridge...) from a netlist which include the logic added by the DFT.

vishalmistry and rca

Where is dft compiler of Synopsys used for this purpose then?

For basic scan connection I directly in DC.

---------- Post added at 18:25 ---------- Previous post was at 18:25 ----------

You could used DC

rca

Is it that you want to mean the dft compiler do the basic scan connection. Is it that dft compiler license is available along with dc?

Regards

I don't know

You should have the special license for DFTC.

What does dft compiler do?

Hi all,

To find the Stuck at faults we have to use only the scan chains path ??

Clarify me if my question is wrong?


--
pavan HS

---------- Post added at 11:35 ---------- Previous post was at 11:34 ----------

sun_ray said:

What does dft compiler do?

Click to expand...

dft compiler adds the dft architecture needed for scan (like number of scan chains, scan compression technique, defining dft signals, creating the protocol file spf), allows you to check dft drcs and fix the violations, and then stitch the scan chains.

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pavanhs said:

Hi all,

To find the Stuck at faults we have to use only the scan chains path ??

Clarify me if my question is wrong?


--
pavan HS

[

Click to expand...

If your design is fully combinational then no need of scan chain to detect stuck at faults.

Scan chains convert difficult to test sequential logic(flipflops) into scan flops, which increase the testability feature of those flops.

ranger01 said:

dft compiler adds the dft architecture needed for scan (like number of scan chains, scan compression technique, defining dft signals, creating the protocol file spf), allows you to check dft drcs and fix the violations, and then stitch the scan chains.

- - - Updated - - -

Click to expand...

But Synopsys DC also insert scan chain and dft feature. What is the difference in this context between dft compiler and dc?

buddy, you might be running a dc synthesis script to get the scan chain inserted into a design. But its being achieved with the help of a DFT compiler license running alongside DC. DC is only for synthesizing the RTL code into gate level netlist. DC alone cannot insert the scan chains..