Query concerning multicycle paths

[jjean]

I have a question regarding multicycle paths.Consider the following scenario.

There is a combo path between two flops clocked by the same clock.The combo path takes more than 5 clock cycles.To handle this properly,

1)In the design ,we introduce a shift register so that the capturing flop is clocked only every 6th clock cycle.Also the data is launched only every 6th clock cycle.The appropriate constraint is :
set_multicycle_path -setup 6 -from regA -to regB
set_multicycle_path -hold 5 -from regA -to regB

So,here,data is launched and captured only every sixth clock cycle.

My question is,alternatively, can we do the following thing?

2)The shift register is removed so that the capturing flop gets clocked every clock cycle.The following constraint is set :
set_multicycle_path -setup 6 -from regA -to regB
set_multicycle_path -hold 0 -from regA -to regB
Also data is launched every clock cycle.
Here what happens is that : For the first five clock cycles of the capturing clock no data is captured.After that,every capturing clock captures a new data.So the advantage is that we can effectively use every clock cycle to launch and capture data.
Please correct my understanding regarding the second alternative.

Thanks,
Jean

 

[iwpia50s]

The problem #2 is that your STA will pass but you data could still be wrong because it is clocked every clock still. Unless your down stream flop is only capturing data every 6 clocks I think you're in trouble.

Added after 3 minutes:

Forget my previous response. If the data is taking 6 clocks to get to the next flop anyway, you should be fine.

 

[littlebu]

Hi Jean

I think you can't get expected result.
firstly, we need understand what is multicycles: is cant finish in one clock cycle. ForExample: 6cycles.
that's mean you need wait 6-cycles to capture comb result use regB. But before you get this result, you need steady input of comb logic. i.e. from 1st-cycle to 6th cycle you can't change output of regA. oherwise comb between regA and regB can't got right result. right?

you can think scenario comb between regA and regB is a adder logic, and in every cycle, adder can complete 1 bit add, but if you change input of adder before finish of all step, you will got a unexpected sum.

Thanks
littlebu