karthik_hr
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Hi,
I am trying to simulate the vectors in general purpose simulation method.
I have a querry while giving the manual input vector file.
I gave input vector file as the vectors generated by the "create_logic_tests" command in ET. The vector files generated was in verilog format.
During general purpose simulation, there was the option of selecting the format of the input vector file in 3 formats i.e STIL, TBDpatt and EVCD.
When I selected EVCD format and gave the verilog format vector file, it threw the following error :-
WARNING (TFS-810): [Severe] Input pattern error encountered.
The circuit was not left in the stability state at the end of
an independent test. The independent test is the Test Procedure
at TBD location 1.1.1.2.1. Invalid test data may result.
The following nets were in error:
hierNetIndex Stab Now NetName
232 1 X Scanmode
143 1 X PRESETn
125 0 X PCLK
[end TFS_810]
Please let me know where am I going wrong in general purpose simulation?
Thank you in advance.
I am trying to simulate the vectors in general purpose simulation method.
I have a querry while giving the manual input vector file.
I gave input vector file as the vectors generated by the "create_logic_tests" command in ET. The vector files generated was in verilog format.
During general purpose simulation, there was the option of selecting the format of the input vector file in 3 formats i.e STIL, TBDpatt and EVCD.
When I selected EVCD format and gave the verilog format vector file, it threw the following error :-
WARNING (TFS-810): [Severe] Input pattern error encountered.
The circuit was not left in the stability state at the end of
an independent test. The independent test is the Test Procedure
at TBD location 1.1.1.2.1. Invalid test data may result.
The following nets were in error:
hierNetIndex Stab Now NetName
232 1 X Scanmode
143 1 X PRESETn
125 0 X PCLK
[end TFS_810]
Please let me know where am I going wrong in general purpose simulation?
Thank you in advance.